Mentor Graphics Enhanced XRAY Debugger Available Immediately For The Tensilica Xtensa Microprocessor
Comprehensive Multi-Core Debugging Environment Now Available For All Xtensa® Processor Configurations
SANTA CLARA, Calif.--(BUSINESS WIRE)--June 17, 2002--
Tensilica® Inc., the configurable and extensible microprocessor
pioneer, today announced the immediate availability of the Mentor
Graphics® XRAY® Debugger for Tensilica's Xtensa IV processor core.
The tool provides a comprehensive debug environment for the thousands
of unique processor configurations that are possible using Tensilica's
powerful Xtensa processor architecture. Using the XRAY Debugger,
designers can simultaneously verify and debug the application and
system software running on one or more Xtensa cores in their embedded
system-on-chip (SOC) designs, as well as other industry-standard cores
supported by the XRAY debugger environment.
"The configurability and extensibility of Tensilica's architecture
is enabling customers to integrate multiple, unique Xtensa cores on an
SOC as an alternative to complex and costly custom logic," said Larry
Przywara, director of strategic alliances at Tensilica. "The
integration of Mentor's XRAY Debugger into the Xtensa development
environment provides a common interface for all stages of the embedded
development process, from simulation to on-chip debug, all built on
XRAY technology. Designers benefit from this industry standard tool
through improved productivity, reduced development risk and faster
time-to-market."
"Multiple processor debug has been a hallmark feature of the XRAY
debugger," said Robert Day, director of marketing, Embedded Systems
Division of Mentor Graphics. "Utilizing Tensilica's Xtensa
architecture, designers gain the advantage of quickly integrating
application optimized processors in their single and multi processor
SOCs and now have the full support of XRAY."
XRAY Debugger Integration and Features
Mentor's XRAY debugger tool is tightly coupled with Tensilica's
Xtensa development environment, providing a consistent feature-set and
user interface for instruction set simulation, hardware/software
co-verification and on-chip debugging. It supports all possible
configurations and extensions of the Xtensa processor without
modification. Key features include the ability to simultaneously
connect multiple Xtensa processors through a single instance of the
debugger; control of the target using hardware, software, complex
macro-based and synchronized multi-core breakpoints; and a C-like
macro language, with an integrated macro editor, to customize
debugging sessions. XRAY supports both the Xtensa XCC and GCC
compilers.
XRAY Debugger in the SOC Design Flow
One of the key productivity advantages of the XRAY Debugger for
Xtensa Processors is the consistent software development interface
across all phases of SOC development. Application development can
proceed before hardware is available by using the XRAY debugger with
an Instruction Set Simulator.
Through the Mentor Graphics Seamless® Co-Verification
Environment (CVE)(TM), the XRAY debugger module for Seamless can be
used to develop software and hardware in parallel, allowing users to
verify system-level software, such as startup code and device drivers,
against a gate-level simulation of the target hardware. And when
hardware is available, connection can be made to the targets via a
JTAG interface with the XRAY Debugger providing complete control over
the processor, with zero target intrusion, ensuring rapid project
completion and shortened time to market.
Pricing and Availability
The XRAY Debugger for Xtensa processors is available for both
Sun® Solaris and Microsoft® Windows NT/2000 platforms and can be
licensed immediately from Tensilica. Pricing starts at $6,000 for a
single seat. XRAY will be delivered through Tensilica's web-based
Xtensa Processor Generator.
About Xtensa
Xtensa is Tensilica's proven configurable and extensible
microprocessor architecture that provides a powerful, integrated
hardware and software development environment with thousands of
configuration options and enables customers to add an unlimited range
of user-defined instructions. As a result, designers can carefully
tune the processor for specific functionality. With an easy-to-use
graphical interface, designers can take advantage of Tensilica's
processor generator to create customized MPU solutions with
specialized functions and instructions. Because these instructions are
recognized as "native" by a complete set of software development
tools, developers can simultaneously tune both application software
and processor hardware to meet specific speed, power and feature
goals.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT - News) is a world leader in
electronic hardware and software design solutions, products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$600 million and approximately 3,500 people worldwide. Corporate
headquarters are located at 8005 S.W. Boeckman Road, Wilsonville,
Oregon 97070-7777; Silicon Valley headquarters are located at 1001
Ridder Park Drive, San Jose, California 95131-2314. World Wide Web
site: www.mentor.com.
The Mentor Graphics Embedded Systems Division is a leading
supplier of embedded software development tools, Real-Time Operating
Systems (RTOSs) and services to more than 50,000 users worldwide. The
company's software development tools include optimizing Microtec® C
and C++ Compilers and the XRAY Debugger. Mentor also provides the
robust Nucleus Real-Time Operating System and code/lab Embedded
Development Suite. Mentor Graphics provides the industry's most
technically advanced solution for RTOS-aware software debugging for
the major processor families and cores used in embedded systems.
About Tensilica
Tensilica was founded in July 1997 to address the fast-growing
market for configurable processors and software development tools for
high volume, embedded systems. Using the company's proprietary Xtensa
Processor Generator, system-on-chip (SOC) designers can develop a
processor subsystem hardware design and a complete software
development tool environment tailored to their specific requirements
in hours. Tensilica's solutions provide a proven, easy-to-use,
methodology that enables designers to achieve optimum application
performance in minimum design time. The Company has over 140 engineers
engaged in research, development, and customer support from its
offices in Santa Clara, California; Burlington, Massachusetts;
Princeton, NJ; Austin, Texas; Raleigh, NC; Oxford, U.K.; Stockholm,
Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is
headquartered in Santa Clara, California (95054) at 3255-6 Scott
Boulevard, and can be reached at 408/986-8000 or via
www.tensilica.com on the World Wide Web.
Editors Notes:
- "Tensilica" and "Xtensa" are registered trademarks belonging
to Tensilica Inc.
- Mentor Graphics and XRAY are registered trademarks of Mentor
Graphics Corporation. All other company or product names are
registered trademarks or trademarks of their respective
owners.
- Tensilica's announced licensees are Avision, Berkeley Wireless
Research Center, Broadcom, Cisco Systems, Conexant Systems,
FUJIFILM Microdevices, Fujitsu Ltd., Hughes Network Systems,
IC4IC, Ikanos Communications, JNI Corporation, Marvell
(Galileo Technology), Mindspeed Technologies, National
Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone
and Telegraph (NTT), Olympus Optical Co., ONEX Communications,
OptiX Networks, Osaka & Kyoto Universities, TranSwitch
Corporation, Victor Company of Japan (JVC) and ZiLOG.
Contact:
Tensilica, Inc., Santa Clara
Kim Alfaro, 408/327-7343
kim@tensilica.com
or
Tanis Communications for Tensilica, Inc.
Joany Draeger, 650/365-3395
joany@taniscomm.com
or
Mentor Graphics
Jennifer Whiddon, 251/661-5770
Jennifer_whiddon@mentorg.com
